Today I am especially pleased to share this exclusive interview with the DeRISC Project. A young project that arises under the umbrella of H2020. That is, under the framework of research and innovation of the European Union. In this case, for the development of computer systems for the aerospace industry.
Undoubtedly, another small step towards a less technologically dependent Europe. And from here I can only hope that it is just one more step, and not the only one. I wish him a bright future, and invite you to continue reading the full interview to discover more about this project with a lot of Spanish flavor…
Architecnología: How did De-RISC Project come about?
DeRISC Project: De-RISC is the project resulting from the need of finding open technologies (hardware and software) for the space and aviation markets which are not affected by export restrictions.The move to lower cost spacecrafts that is also taking place requires to leverage technologies used in other high volume markets and this fuels a need to shift to architectures present in these larger commercial markets. Additionally, in the last years, an open-source Instruction Set Architecture (ISA) called RISC-V is becoming very popular and it is attracting the attention of many companies and research institutions in the aerospace domain and other high volume markets. RISC-V solves the need in these markets offering a unique opportunity to develop EU-based products for the aviation and space domains with no dependence on external technology or licenses.
The consortium of De-RISC identified this opportunity and started this project whose objective is to introduce a hardware and software platform based around the RISC-V ISA.
AT: Your focus is on critical systems, such as aviation and space. What is the biggest challenge you are facing?
DRP: Indeed, critical systems present a particular challenge mainly in the adoption of technology based on RISC-V in the space industry. Technically, the most important challenge is related to achieve the predictable behaviour required by critical space systems when powerful architectures with many processors are used (what is called multicore systems) as is the case of the computer platform developed in the project. This is the main obstacle hindering the qualification of the hardware and software to meet aerospace standards.
AT: You work with IP cores of the Swedish Cobham Gaisler. If I remember correctly, the LEON developed for ESA used the ISA SPARC V8… But that has changed in the new NOEL-V. How has the openness of RISC-V contributed to issues such as security and other key factors for critical systems?
DRP: The open nature of RISC-V is what will allow the space industry to spin-in developments in fields such as security. The openness and transparency that RISC-V offers, provide easier ad-hoc improvements or modiﬁcations for security, as detailed information is already available. This avoids the need to design everything from the scratch and, consequently, increases reusability and reduces the resources, time, and complexity required to design secure and trusted systems. RISC-V ISA also has a very complete set of security mechanisms based on Privilege rings, Physical Memory Protection, User-mode Interrupts and exception handling. Additionally, this open ISA is also backed by big tech companies which are members of the RISC-V Foundation, something that re-emphasizes the security requirements that RISC-V offers.
AT: What is the collaboration with the BSC based on?
DRP: Building on its experience validation of embedded and high-performance systems, BSC leads the definition of the validation strategy, contributes to the hardware validation, and leads the assessment of the fitness of the platform across multiple domains, ensuring robustness and observability to the HW. Additionally, they provide key technology to increase the time predictability of the multicore architecture while preserving high performance which is a major challenge as we mentioned earlier.
AT: XtratuM, by fentISS, is specially designed for Real-Time embedded systems based on SPARC and ARM. How is the port for RISC-V being made? I mean, do you have any feedback with fentISS, are you doing it yourself,…?
DRP: The modular design of XtratuM allows for changing the processor architecture, so the porting to RISC-V is done similarly to the porting to any other architecture.
fentISS is continuously reporting to the consortium the progress on the porting through the monthly regular meetings and it is in permanent contact with Cobham Gaisler to solve the technicall issues that usually come up. fentISS has worked hard during the last months in the porting so we currently have a prototype running on the last version of NOEL-V in the Xilinx Kintex Ultrascale FPGA KCU105 board. We plan to show some demos in upcoming events.
AT: XtratuM, being a bare-metal hypervisor eliminates the need for a host operating system, one layer less. Does this answer questions of reliability or just performance? Maybe both?
DRP: The main purpose of XtratuM is not to increase performance but to guarantee the non-interference from different applications running on the same computer which is essential in safety critical systems. One of the advantages of XtratuM compared to other solutions is that its high level of optimization guarantees a minimum performance penalty paid to achieve higher levels of criticality. Besides that, XtratuM allows different “guest operating systems” to be used on top. One can have an application running our ARINC-653 compliant LithOS operating system to implement critical functions whereas other applications can run Linux for less critical functions.
AT: The hypervisor will have a modular app from Thales Research & Technology. What is the purpose of this app? And what kind of guest operating systems will it be? Real-Time Linux with apps for TM/TC?
DRP: As in any European Commission funded project, a use case is required to validate the technology developed from the user’s viewpoint. This is the main purpose of the three use cases that will be eventually implemented in the project. The three use-cases will validate the features of the NOEL-V processor and XtratuM XNG: A low-level benchmark execution, the LVCUGEN framework and a Command & Data Handling Platform.
The first use case to develop will be the execution of low-level benchmarks both, bare metal execution and XNG XRE (XtratuM Runtime Environment, a minimal system to run applications with no guest operating system). This use case will validate the basic functionality of the architecture and will provide simple performance estimation to compare the architecture performance to other solutions available on the market. The several levels of such benchmark applications will include the checking for the compliance with RISC-V standards, some providing single-value performance scores, and the evaluation of the impact of the memory hierarchy and shared hardware resources on safety and security requirements.
The second use case will be the on-board satellite software stack, which will use the LVCUGEN framework. LVCUGEN is a generic on-board framework developed by the French National Center for Space Studies (CNES) using XtratuM and LithOS. The purpose of this framework is to provide common on-board functions which are re-usable for different missions to minimize the satellite integration effort and ease the testing activities. Through LVCUGEN, critical partitions performing typical operations of a satellite (such as ground-to-satellite communications, positioning, mission control, etc.) and non-critical partitions performing payload computation, such as image compression.
The last use case will be a command & data handling subsystem. The TM/TC (telemetry and telecommand) application offers the opportunity of a large range of processing characteristics, exercising the processor and the software environment in a complete way. This use case consists of a simplified satellite platform modeling: the satellite’s telecommand and telemetry function; the management of generic peripheral devices; the management of large file transfers; and the execution of legacy Star Tracker code. This platform has been previously used in other projects to evaluate the usage of multi-core processors in the context of mini and micro satellite constellations using a GR740 SoC and a previous versions of XtratuM. Once adapted to the De-RISC platform, we will be able to compare the performance of both solutions.
These aerospace use cases will be executed as part of the De-RISC project to assess the safety and the security properties of the hardware+software project platform..
AT: If I am not too wrong, satellite systems, rovers, and ships, used very primitive processors hardened against radiation (RH), with years of longevity and tested (I guess for reliability issues). For example, the Z80, RCA 1802, 8085, 8086, RAD 750 (PowerPC 750), Mongoose-V (MIPS R3000), etc. Nothing to do with the cinema and the advanced systems of board that can be seen in certain movies of science fiction. But RISC-V is a very young ISA, and so are Cobham Gaisler’s SoCs. What is the key to a reliable system for this type of application? I suppose it will be a mix between simplifying all the systems and subsystems as much as possible, implementing fault-tolerant systems, and test, test and more test.
DRP: The main problem faced by the electronics in space is the lack of tolerance to the radiation present in the space environment. This makes it difficult to increase the density of the silicon used on-board and this is the reason to use older processor architectures as compared to the architectures used on ground applications. However, the hardware technology developed by Cobham Gaisler in their LEON-based MPSoCs and in the more modern NOEL-V ones, is rapidly increasing the performance of the processors for space applications. LEON processors have already a significant space heritage in missions of very different profiles (i.e. LEO, GEO or deep space) and they have proved the maturity of the technology. NOEL-V will go a step further and it will guarantee a solid roadmap for the hardware technology of the company.
The second part of the answer is indeed connected to the need to meet the hardware and software qualification standards to decrease the risk associated with new technologies. The standard dveloped in Europe is the ECSS (European Cooperation for Space Standardization), and it covers a whole development for space, including hardware and software robustness, safety and security. To meet this standard, the project has a set of validation tasks which will ensure the right level of quality for the project platform These tasks include specific functional tests to validate each of the XtratuM features, performance tests based on microbenchmarks to assess corner performance and power cases, as well as regular benchmarks and the use cases for KPI assessment.
AT: It’s great to see the growing interest in RISC-V. For example, some time ago I read a news item about a project based on RISC-V to Venus. If anything can be advanced… do you already know of any important space mission, or future application, in which your work will be used?
DRP: It is too soon to determine the future commercial use of De-RISC. We have already presented our initiative to some national space agencies receiving good feedback and interest about it. However, new technologies require relatively long time periods to fly in a mission. ESA specialists foreseen from 1 to 3 years for the adoption of RISC-V in rad-hard FPGAs and between 3 and 8 for the adoption in rad-hard ASICs SoC cores. We anticipate that first missions will be related to New Space minisatellites which can tolerate somehow lower quality levels and demand shorter time-to-market.
AT: I understand that the fact that Europe lost ARM was a hard blow. It seems that the world is becoming somewhat more hostile, with the restrictions and technological wars that we have known lately. That, coupled with Europe’s serious dependence on the US and China, especially in hardware, is a problem. Horizon 2020 is trying to reverse that problem. How do you see the European technology landscape in the medium term?
DRP: The European Commission has been making steps towards the technology independence of Europe for a long time. An example of that is precisely De-RISC, where the consortium collaborates on the development of that technology independence from the US or China on both hardware and software. Thanks to this kind of projects and the initiative of the European Commision to find solutions within European borders, Europe will be able to be absolutely independent in the long term and the reasons to choose one or another technology will depend on other factors.
AT: Some time ago, Andrew Waterman confirmed to me by email that RISC-V intended to move to Switzerland. A key move to avoid certain restrictions. Now RISC-V has almost saved the hardware of the Old Continent, and is the basis for some interesting European projects such as yours or the accelerator of the EPI project. In your case, the objective is to replace foreign technology systems with European technology. How have you lived all these wars and movements?
DRP: Large European companies have been progressively more sensitive to export restrictions from the USA or difficulty to access Chinese technology. On the other hand, the European Agencies (ESA, CNES, DLR, ASI,…) and the European Commission have been very conscious of the problem for years but a common European policy is often relegated by the countries for other national interests. In the particular cases of the technologies of concern to De-RISC the dependence of the USA is very accused. On the hardware side, efforts like De-RISC and others attempt to keep up but a more unified approach would be required to progress faster in European non-dependence.
AT: And finally, Will De-RISC Project only be limited to aerospace projects or do you plan to go beyond that as well?
DRP: The primary De-RISC target is the space and aviation markets and within the duration of the project, the consortium will not focus on other markets. However, the technology developed in the framework of De-RISC can be applicable to other safety critical markets, such as automotive, railway, energy or medicine. The project partners will be attentive to opportunities in these adjacent markets beyond the project end.
AT: Thank you! And Good Luck!