Philippe Notton is the CEO and founder of SiPearl, the startup created around the EPI (European Processor Initiative) project. Today, I have the fortune to share with you this interview in which you can discover some interesting information about this fantastic European project.
If you want to know more about Philippe and the EPI project, I invite you to continue reading…
Architecnología: When did the EPI project start?
Philippe Notton: EPI officially started on Dec 2018 after 12 months of preparation.
AT: How were the members of the consortium (BCN, Chalmers, Infineon, BMW,…) chosen?
P.N.: Based on their expertise and to have a self-sufficient Consortium.
For HPC for instance, we have the full chain from IP designers – chip makers – software providers – machine makers – users of the machine with datacenters – application providers.
For automotive we have the full chain also from chip and software vendors – to equipment makers and car makers.
AT: How are you trying to finance the project under SiPearl? In addition to the 80 million…
P.N.: The EPI public budget of 80M€ is not sufficient to cover all the expenses needed to build such a chip. Therefore, SiPearl has to raise more than 100M€ on the market (equity mainly).
AT: Why ARM for GPPs if it is owned by SoftBank? I suppose because of development time issues, starting from IP cores. Do you think that a microarchitecture from scratch based on RISC-V ISA would be viable?
P.N.: ARM spent 10 years to develop an ecosystem for DataCenter and HPC. They are now a serious challenger to x86. RISC-V will have to follow the same path. Years to spend to mature the cores (IPs) and the SW ecosystem, and for HPC this cannot be done in 2 years.
AT: Will the Marenostrum (2025) have only EPI processors? I guess it will be heterogeneous computing with GPGPU too, right?
P.N.: The preparation of procurement of MareNostrum and other EU systems is under way, and once it is publicly announced it will provide more details.
AT: Before 2025, Will there be clusters running with EPI chips and coexisting with current Intel chips? That is, a kind of transition…
P.N.: I’m back to your question of heterogenous architecture. HPC can be made of multiple components. Therefore, we can have a mix of Intel, EPI and NVIDIA for instance, to prepare the transition to a full EPI General Purpose CPU / EPI – Accelerator for instance. Everything is possible.
AT: Why TSMC and not GlobalFoundries? At least GF has a factory in Dresden, Germany.
P.N.: Global Foundry is in Europe but does not offer technology more advanced than 22nm. ST-Crolles in France offers down to 28nm. EPI processor targets state of the art technologies and extra IPs like memory controller or PCI are only available in processes beyond 7nm.
Density needed and ratios performances/watt needed for this class of computing can only be achieved beyond 7nm. I’ll be very happy to use a fab in Europe… when available.
AT: Do you also consider investing in a European foundry? It is something in which we are also at a disadvantage vis-à-vis Asia and the USA.
P.N.: As said, there is no foundry in Europe for this class of design.
Budget needed for a foundry is far beyond EPI scope (>$20B for last TSMC fab).
Our approach is also fabless, so we have no reason (and it will not be realistic) to invest in a fab.
AT: The brain-drain of talents is also a big problem in Europe. Have you been able to get the right people back from Silicon Valley?
P.N.: I was a bit nervous before starting the recruitment due to “competition” with other chip makers to get the best talent, but finally our project is very exciting for engineers; with top notch technology and we got number of CV’s from around the globe, including US and UK.
AT: Can you advance any of Rhea’s final design data? (Manycore, chiplets, PCIe lanes, core count, transistor count,…)
P.N.: We can only precise at this stage that it’s HBM2 and PCIe Gen 5 based. Other elements can be discussed under NDA with SiPearl. Arm will also communicate later this year about the core we are using.
AT: What is demanding the most effort, time and resources? (Design of the microarchitecture, firmware,…)
P.N.: Using ARM ecosystem helps to reduce the SW development load, with a fully loaded ecosystem. Optimization is needed but not on the critical path.
Designing such a complex chip in 7nm needs lots of engineering and computing resources.
AT: Why only HPC and automotive? Don’t you plan more sectors in the future?
P.N.: EPI roadmap is covering edge and datacenter as the next steps, which means basically everything from connected mobility to the HPC. So, we expect to be part of the full data chain.
AT: By the way, BMW is involved in the development. Will other European vehicle manufacturers be able to use your technology?
P.N.: EPI & SiPearl technologies are not exclusive to EPI members. So, others vehicle manufacturers are welcome and are talking to us of course. The car industry has now the same issues in terms of sovereignty and control of the data, and they need some local strategic components. It’s already in place for ECU and power control, but not for the main digital part.
AT: Will we see EPI technology in data centres outside Europe or only in Europe?
P.N.: EPI technology is not exclusive to European data center. We have raised already a worldwide interest with the key server vendors. They understood that our technology will be quite central in Europe. Entering their product lines means that they could ship us later on everywhere on a WW basis; At the end, performances matters, and we have good expectations.
AT: People are worried about environment and climate change. How can efficient EPI design help this issue? HPC uses a big percentage of the world’s energy…
P.N.: That’s true, HPC is power hungry, but moving to deep node submicron gives the best ratios in terms of performance per watt. So, we are very energy efficient.
AT: What about security? Another important question, especially for HPC machines that handle such important data. We have seen what has happened to Intel’s numerous vulnerabilities.
P.N.: A significant part of EPI budget is on security, under the lead of Prove & Run. So, yes, the chip will include lots of security mechanisms, European made, to protect the data. I cannot comment Intel vulnerabilities, but they manage a huge volume and a large footprint, so they are widely exposed. It’s a sign of success.
AT: Open source and Linux is key to your platform, isn’t it?
P.N.: Yes, no doubt about it, and here also the ARM ecosystem is helping a lot, and the RiscV ecosystem once mature for HPC will be very useful.
AT: I’m very excited about this project. I’m following it with great enthusiasm. When do you think we will be able to see the first results (benchmarks, die shots,…)? If they are going to be public…
P.N.: We were supposed to disclose some elements at the EPI forum in March, this event has been delayed to Q1/2021. Stay tuned.
AT: I always cross questions between interviewees. Silvia Barrera is a Police Inspector specialized in cybersecurity and cybercrime and she wants to ask you this question: “What types of AI algorithms have been the bigger challenge? And How will they help to the future supercomputing?”
P.N.: I let this question to our AI experts…