Matthew Venn: Exclusive Interview for AT
Today I will share a very interesting interview with Matthew Venn. A tech-savvy communicator with an extensive background in the software and hardware industry. He was CTO of Sygma, electronics engineer at Bristol Braille Technology CIC, electronics engineer an sales at Symbiotic EDA, and current CSO of YosysHQ.
This electronics engineer has knowledge of Python, electronics engineering, about EDA environments for electronics development, Verlog hardware description language, etc. In addition, he has an interesting teaching project, such as the Zero To ASIC course…
Architecnología: I always ask at the beginning: Who is Matthew Venn? (Describe yourself, please)
Matthew Venn: Hi, I’m a science communicator and an electronics engineer. I’ve been more focussed on the engineering side until this opportunity to create a course about ASICs happened and now I’m concentrating more on the communication.
AT: When and how did you start being passionate about technology?
M.V.: I’ve always wanted to know how things worked. Actually when I was a teenager I thought I would one day understand how everything works! Then as I grew older I realised how huge the universe is and how there would be no way to understand it all. I still struggle with this balance between focus on one topic and interest in everything..
AT: Do you have a reference? Someone who has inspired you?
M.V.: My dad and my uncles encouraged me with electronics and mechanics by giving me old bits of hardware to take apart or build. I’m sad to say I never really experienced a great technology teacher, maybe that’s why I’m drawn to that myself.
AT: What tools do you usually use for ASIC development?
M.V.: People often confuse me with an ASIC expert. I try to make it clear on my website and videos that I’m learning as I go. I think that’s one of the things that makes my story interesting. I only just started learning ASIC technology when the open source tools were released last year. Otherwise it would always have remained out of reach. So to answer your question, I have only ever used the open source tools: OpenLANE which surrounds the core tools called OpenROAD.
AT: What should a student registering for the Zero To ASIC course expect? And when will the Spanish version be available?
M.V.: They should expect a great course with lots of interesting material, a supportive community and plenty of help if they get stuck. We are working on a Spanish version of my #remoticon talk and then we’ll gather emails of interested people. If there is enough interest we’ll translate the course.
AT: Do students need a certain level of knowledge to start the course?
M.V.: Not related to ASICs or FPGAs or digital design. But I do use Linux, git and make a lot, so some familiarity with those tools would be useful.
AT: With what students learn, Could they adapt any design to any manufacturing node?
M.V.: Theoretically yes, but practically no, because currently the only PDK we have is the Skywater 130nm PDK. As more PDKs are added then we will get access to those other sizes.
AT: Verilog vs VHDL vs Chisel. Your opinion… And Why did you choose Verilog for the course?
M.V.: I chose Verilog because it’s best supported by open source tools for simulation, verification and synthesis. Yes I could have chosen nMigen or Chisel. Or maybe even VHDL supported by GHDL, but I wanted to keep things simple. Personally I don’t care, whatever people find suits them.
AT: What is most important when choosing an EDA?
M.V.: For me, price! I don’t have 100k a year to spend on a license, and obviously that would make the course impossible.
AT: Are there major shortcomings of open source EDAs compared to proprietary solutions, such as Cadence software or developed in-house by large semiconductor companies?
M.V.: I’m sure there’s a lot, but I can’t comment too much because I don’t have experience with the industry standard tools. You can see some interesting interviews on my youtube channel. Tom Spyrou and Thomas Parry for digital and analogue respectively. They both have lots of industry experience and have talked a bit about the differences..
AT: What is the most critical stage of chip development?
M.V.: I’m not sure, but I would guess once you have decided to make a chip in the first place, then it would be verification. That’s because of the long lead times and high costs involved in the process.
AT: Hardware trojan: What can be done in the early design stages of a chip to avoid it?
M.V.: I don’t know. I think hardware trojans of the type I’ve been exploring are mostly theoretical. Some people replied to me saying that for large and expensive chips, they require that they verify the masks themselves against the final files. I think that’s probably only possible for very large companies, but then again those are probably the ones in danger of such a targeted attack. There are some interesting papers about this topic so I would suggest if this area interests you then get stuck in and read some papers.
AT: In many interviews I usually ask about safety issues and also about environmental or energy efficiency issues. What can be done during the design of a chip to make it more efficient (in addition to simplifying)?
M.V.: I don’t know, I’ve never thought of that aspect. Energy efficiency is of huge importance to modern devices, but to be honest I’m focussing on much older processes where we usually have more leeway. Also, my main focus is currently on teaching and less about the practical business of making chips that have a market value.
AT: And finally What books would you recommend to those who want to learn about VLSI design?
M.V.: I have been enjoying studying ‘CMOS VLSI design‘ by Weste/Harris. I also liked ‘Introduction to VLSI systems‘ by Mead & Conway – it’s old but still interesting to read. I’ve put both these books and other resources on this page.
AT: Gracias Matthew! Disfruta del sol de Valencia…🥘