Calista Redmond of the RISC-V: exclusive interview for AT

Today I have the pleasure of sharing with you one of the most eagerly awaited interviews. A interview with Calista Redmond of RICS-V. A very interesting project that I’ve been following for some time. A project that has a lot to do with Europe’s non-technological dependence.

If you want to know more about RISC-V, read the complete interview…

Complete interview

The RISC-V ISA was created after the low success of, for example, OpenRISC. Wasn’t this taking a big risk?

Back in 2000, when the OpenRISC project took off, it appeared that the market didn’t quite have the appetite for open and freely available ISAs and associated processor designs. At that time, the industry had accepted Intel as the dominant ISA for servers and PCs, at the same time, ARM was gaining traction in mobile. The number of workloads requiring custom processors simply was not diverse enough and the business cases were too challenging to close based on anticipated volumes. As computing workloads continue to rise thanks to artificial intelligence, machine learning, the Internet of Things and VR/AR, there is a growing demand for custom processors to meet the power and performance requirements of specific applications. In parallel, RISC-V is bringing to light a royalty free business model, with a highly modular technical design. Together, these factors have cultivated the perfect time and place for open, custom processor design. RISC-V is enabling the industry to optimize designs for today’s computing requirements and innovate faster.

Other ISAs are years ahead in development. RISC-V is still very young. Do you think this could affect the adoption?

RISC architectures are many decades old, it is not the technology that is new, but the modular approach and the disruptive business model. One defining characteristic of RISC-V is that the RISC-V base ISA is simple and small, with over 20 ISA extensions, each focusing on a specific functionality, such as bit manipulation, user-level interrupts, atomic instructions, single- and double-precision floating point, integer multiplication and division. The RISC-V ecosystem also encouraged developers by adding custom instruction sets without any kind of approval process.

Early RISC-V adoption is evident in two areas, first in easy to plug and play microconctrollers that work together with existing architecture choices. Second, we’re seeing innovation on new workloads such as embedded, IOT, AI, and consumer devices. We anticipate that a second wave in enterprise and mobile will occur as the industry gains experience with RISC-V and the ecosystem continues to grow.

Today, we’re already seeing legacy ISAs and RISC-V ISA on the same core, so there is a trend where companies are leveraging both proprietary and open source standards.

The RISC-V ecosystem is one of the most dynamic communities I’ve seen to date. Over the last few years, the membership has grown exceptionally fast and includes a broad mix of organizations in different industries. RISC-V accelerates development time, while reducing strategic risk and overall costs, enabling companies to reap a variety of benefits from the free and open ISA.

How did you react when the European Processor Initiative (EPI) announced its plans to leverage the RISC-V ISA?

We are very excited that the EPI is utilizing RISC-V. The EPI project introduces exciting new possibilities for innovation – especially for segments like HPC and AI that are undergoing compute disruption. By bringing the industry a new level of free, extensible software and hardware freedom on architecture, the EPI project gathered together 26 partners from 10 European countries with the mission to develop and bring to market low power processor technology. RISC-V specifically has been highlighted for compute acceleration.

Do you have any kind of collaboration or feedback with EPI?

rAs part of the EPI project, the Accelerator stream is working to develop and demonstrate European processor IPs based on the RISC-V ISA. The accelerator will be designed for high throughput and power efficiency within the GPP chip. Using RISC-V enables the program to leverage open source resources at the hardware architecture level and software level, as well as ensuring independence from non-European patented computing technologies.

In addition to focusing on solutions for the HPC market, the EPI project also targets the autonomous vehicles industry and the data center and servers market. As processing demands for these applications are skyrocketing – for example, as cars become more autonomous and capable of real-time decision making – novel silicon approaches are required to power the next generation of smart devices and machines.

We have also recently launched the HPC Special Interest Group together with the Barcelona Supercomputing Center to support HPC focused initiatives in Europe as well as globally as our membership seeks high performance computing across a variety of domains with RISC-V.

When do you think the first RISC-V-based servers and supercomputers will arrive?

In collaboration with the EPI project, experts in the silicon and HPC industries expect to create a new family of low-power European processors, aimed at high-performance computing, by 2021. Six months after starting up, the European Processor Initiative delivered its first architectural designs to the European Commission, completing the first phase of the project. Initial products are expected in two years, with the aim of giving Europe the third fastest supercomputer in the world.

The EPI project includes experts in the silicon and HPC industries are collaborating to develop the first European HPC SoCs and accelerators, with the goal of creating a processor for the Exascale machine based on European technology. This Exascale supercomputer will be capable of one exaflop of performance –around a million times faster than typical desktop computers – which has the potential to significantly advance AI and scientific research.

And for home systems? Do you think there will be RISC-V-based devices to replace the current ARMs and x86s?

The RISC-V ecosystem is poised to significantly grow over the next five years. Semico Research predicts that the market will consume a total of 62.4 billion RISC-V CPU cores by 2025! By that time I look forward to seeing many new types of RISC-V implementations including innovative consumer devices, industrial applications, high performance computing applications and much more.

The Foundation’s goal is to accelerate industry adoption of RISC-V for the shared benefit of the entire community of stakeholders. We’ll continue to do that by driving progression and closure on standards and technical deliverables, making it easier for companies to implement RISC-V cores in their products. Another priority is growing the overall member community across stakeholder areas and deepening community engagement. We will do this by focusing on expanding the ecosystem across industries and geographies, along with offering more support and educational tools so operating systems, hardware implementations and development tools can scale faster.

About performance. What are the special qualities of RISC-V? How a processor can win the battle against ARM, x86, SPARC, POWER,…? With more cores per die?

There is no doubt that RISC-V is in a very strong technical position, building on decades of practical architectural experience and attracting support from across the industry. Chinese tech giant Alibaba announced the fastest RISC-V processor to date in July 2019, running at 2.5 GHz with 40 percent more performance than reference RISC-V designs. Alibaba’s investment in RISC-V is an indicator of an industry trend, as the open source and effectively royalty-free RISC-V design is an effective means for hardware designers.

For twenty first-century hardware designers, both x86 and ARM chips have a major drawback: cost. The core RISC-V specification is of patent encumbrance, and is licensed under Creative Commons. The key point is that the architecture is extensible without losing efficiency. RISC-V aims to break up the proprietary hold on processor design in exactly the same way that open-source software liberated huge swathes of the industry.

What are the benefits of RISC-V?

1. Unlocks architecture and enables innovation. RISC-V is a layered and extensible ISA so companies can easily implement the minimal instruction set, well defined extensions and custom extensions to create custom processors for cutting-edge workloads.
2. Reduces risk and investment by enabling companies to leverage established and common IP building blocks with the development community’s growing set of shared tools and development resources.
3. Provides the flexibility to create thousands of possible custom processors. Since implementation is not defined at the ISA level, but rather by the composition of the SoC and other design attributes, engineers can choose to go big, small, powerful or lightweight with their designs.
4. Accelerates time to market through collaboration and open source IP reuse. RISC-V not only reduces development expenses, but also enables companies to get their designs to market faster.

 What are the main challenges for the RISC-V for 2020?

RISC-V is building on the foundation we’ve laid in our first five years through a focus on six key programs in 2020 and beyond, cultivating and multiplying the value of membership and RISC-V adoption in the industry.

1. Technical deliverables. We’re driving with discipline and collaboration on more than 20 work groups and committees.
2. Compliance and verification. We released the first RISC-V compliance suite at the inaugural RISC-V Summit in December of 2019 and will continue to roll out tools and resources to certify and ensure compliance and interoperability for RISC-V implementations.
3. Visibility. We’re growing the voice of the RISC-V community to amplify the strides of the Foundation as well as the adoption across the industry through the efforts of our diverse community.
4. Learning and academia. We’re building a catalog of curriculum from universities and professional training organizations to provide resources to educators and learners alike in deepening and growing the industry talent on RISC-V.
5. Advocacy. We’re growing meetups beyond the 2,400 members in 20 meetups today to engage the engineer community to connect to one another, build skill, and overcome challenge through collaboration.
6. Marketplace. We have grown our listing of available cores and SoCs online, and we’re continuing to bolster this to ensure we route interest to products and services as efficiently as possible, as key resource for all things RISC-V.

 What’s the role of the RISC-V Foundation in promoting the RISC-V ISA?

The RISC-V Foundation’s role is to build an open, collaborative community of software and hardware innovators while directing the future development and adoption of the RISC-V ISA. Our top focus is driving the technical collaboration to enable a broad and deep ecosystem of RISC-V extensions, tools, and resources to bolster adoption. To gather the community together, each year the RISC-V Foundation hosts global events to discuss current and prospective RISC-V projects and implementations, commercial and open-source implementations, software and silicon, vectors and security, applications and accelerators, simulation infrastructure and much more. We also actively promote independently hosted Meetups and events centered around RISC-V.
We encourage organizations, individuals, and enthusiasts to join our ecosystem and together enable a new era of processor innovation through open standard collaboration.

There are three main issues that concern me. One is security. How can RISC-V help in this case?

Processor security is one of our top priorities and the RISC-V community is embracing a completely new platform to help provide the necessary simplicity to thwart malicious software security attacks, while also enabling designers to assess the security of the open-source architecture for themselves. There are over 30 plus RISC-V member companies developing hardware secure CPU solutions. RISC-V has hosted a RISC-V Security committee as a strategic and pragmatic collaboration point for the RISC-V community. This committee provides guidance as well as oversees key workgroups on the topic of security and related concerns. Our role in securing computer architecture and processors will only grow.

The other is energy efficiency, especially now with the climate change alert. Data centers consume a lot of energy. How can RISC-V help in this other case?

Open and scalable architectures enabled by RISC-V are important and attractive as they will help accelerate the deployment of data-centric applications for Big Data and Fast Data environments. Bringing compute power closer to the data minimizes the movement of data at the edge thus optimizing processing, enabling smart machines and artificial intelligence, and providing a new class of low-power processing designs for the next generation of applications. In present applications, RISC-V has been viewed as a great low power alternative that has great application in consumer devices such as wearables from Huami as well as embedded devices and IoT.

And finally, technological dependence in Europe. That’s why projects like EPI have been launched. Could the USA government limit the use of ISA RISC-V for other countries in any way? Do you plan to move the foundation to Europe (Switzerland)?

Over the last year the RISC-V community has reflected on the geo-political landscape and we have heard concerns from around the world that investment in RISC-V must come with IP access continuity to ensure a long-term strategic investment. It is important to first understand that the license of RISC-V is a global license, not governed by any one jurisdiction so the incorporation of RISC-V does not matter. Open Source license, just like open standards, are held at a global level – not at a geographic level.

As an organization, we abide by the laws of the jurisdiction of our incorporation. Our planned incorporation in Switzerland has the effect of calming concerns of political disruption to the open collaboration model with no effect on the open source license of our technical elements. The RISC-V foundation does not maintain any commercial interest in products or services as a non-profit, membership organization. There have not been any export restrictions on the Foundation in the US and we have complied with all US laws. The move does not circumvent any existing restrictions, but rather alleviates uncertainty going forward.

The Foundation is not incorporating in Switzerland based on any one country, company, government, or event. This move is reflective of community concern and managing strategic risk for our community investing in RISC-V for the next 50+ years. The jurisdiction of the Foundation has bearing only on the Foundation’s ability to facilitate global collaboration. The move reduces concern that a government would

How will quantum computing and the limits of silicon tech affect RISC-V?

RISC-V is not presently engaged in any quantum computing initiatives…